1. Field of the Invention
The present invention relates to a semiconductor test circuit, and more specifically, to a semiconductor test circuit for testing a semiconductor memory device having a write mask function.
2. Description of the Background Art
Conventionally, a system LSI having a logic circuit and an eDRAM (embedded DRAM) merged is being developed. Between the logic circuit and the eDRAM, simultaneous inputting and outputting of several hundred (for instance, 256) data signals is made possible in order to achieve improved data transfer rate. In addition, one write mask signal is provided for every prescribed number (for instance, eight) of data signals, and it becomes possible to inhibit the rewriting of data signals of the corresponding prescribed number of memory cells by controlling the write mask signal. Moreover, in the system LSI, a test circuit is provided for testing with few test pins whether each memory cell within the eDRAM is normal or defective.
FIGS. 17A and 17B are circuit block diagrams representing the main portion of the test circuit in such a system LSI. For simplicity of the drawings and description, only the portion related to 16 data signals TDQ0 to TDQ15 will be described.
In FIGS. 17A and 17B, the test circuit includes data scramble registers 80.0 to 80.15 and EX-OR gates 81.0 to 81.15. An external write data signal EDI is input to one input node of each of EX-OR gates 81.0 to 81.15. Output signals xcfx8680.0 to xcfx8680.15 from registers 80.0 to 80.15 are respectively input to the other input nodes of EX-OR gates 81.0 to 81.15. Signals xcfx8680.0 to xcfx8680.15 are set, for instance, alternately to the logic high or xe2x80x9cHxe2x80x9d level and the logic low or xe2x80x9cLxe2x80x9d level in advance. Output signals from EX-OR gates 81.0 to 81.15 become internal write data signals TD0 to TD15, respectively.
When external write data signal EDI is set to the xe2x80x9cHxe2x80x9d level, data signals TD0 to TD15 alternately attain the xe2x80x9cLxe2x80x9d level and the xe2x80x9cHxe2x80x9d level according to output signals xcfx8680.0 to xcfx8680.15 from data scramble registers 80.0 to 80.15. When data signal EDI is set to xe2x80x9cLxe2x80x9d level, data signals TD0 to TD15 alternately attain the xe2x80x9cHxe2x80x9d level and the xe2x80x9cLxe2x80x9d level according to output signals xcfx8680.0 to xcfx8680.15 from data scramble registers 80.0 to 80.15. Data signals TD0 to TD15 are respectively written into 16 memory cells MC0 to MC15 designated by an address signal. It is, however, made possible to inhibit writing of data signals TD0 to TD7 and/or TD8 to TD15 by two write mask signals.
In addition, the test circuit further includes EX-OR gate circuits 82.0 to 82.15, determination circuits 83.0 to 83.15, and a determination result compressing circuit 84. An external expected value EEX is input to one input node of each of EX-OR gates 82.0 to 82.15. Output signals xcfx8680.0 to xcfx8680.15 from registers 80.0 to 80.15 are respectively input to the other input nodes of EX-OR gates 82.0 to 82.15. EX-OR gates 82.0 to 82.15 respectively output internal expected values IEX0 to IEX15. External expected value EEX is input in synchronization with read data signals TQ0 to TQ15, and its logic level is set to be the same as the logic level of external write data signal EDI upon writing of write data signals TD0 to TD15 corresponding to read data signals TQ0 to TQ15. Thus, internal expected values IEX0 to IEX15 respectively become the same as internal write data signals TD0 to TD15.
Determination circuits 83.0 to 83.15 respectively receive internal expected values IEX0 to IEX15 and read data signals TQ0 to TQ15. Determination circuit 83.0 determines whether the logic level of read data signal TQ0 matches the logic level of internal expected value IEX0, and causes a signal JG0 to attain the xe2x80x9cLxe2x80x9d level that indicates that a corresponding memory cell MC0 is normal when the logic levels match, and causes signal JG0 to attain the xe2x80x9cHxe2x80x9d level that indicates that the corresponding memory cell MC0 is defective when the logic levels do not match. Other determination circuits 83.1 to 83.15 are the same as determination circuit 83.0.
Determination result compressing circuit 84 receives output signals JG0 to JG15 from determination circuits 83.0 to 83.15, and causes a signal Q0 to attain the xe2x80x9cLxe2x80x9d level when signals JG0 to JG15 are all at the xe2x80x9cLxe2x80x9d level, and causes signal Q0 to attain the xe2x80x9cHxe2x80x9d level when at least one of signals JG0 to JG15 is at the xe2x80x9cHxe2x80x9d level. Thus, the detection of the logic level of signal Q0 allows the detection of whether 16 memory cells MC0 to MC15 are normal or not.
In the case, however, where write mask control is performed with respect to data signals TD0 to TD7, for instance, during a write operation, the data signals of memory cells MC0 to MC7 corresponding to data signals TD0 to TD7 will not be rewritten so that, even if the logic level of external write data signal EDI during the write operation is made to be the same as the logic level of the expected value EEX during the read operation, internal expected values IEX0 to IEX7 and write data signals TD0 to TD7 would not necessarily match. Therefore, conventionally, a test that accompanies the write mask control during the write operation did not allow the use of a time reducing technique such as the above-described multi-bit test and thus involved the problem of a longer test time.
Thus, the principle object of the present invention is to provide a semiconductor test circuit capable of performing a multi-bit test even when a test pattern is written using a write mask function.
A semiconductor test circuit according to the present invention is a circuit for testing a semiconductor memory device having a function simultaneously to perform writing/reading of data signals of a plurality of memory cells designated by an address signal and having a write mask function to inhibit rewriting of the data signals of the plurality of memory cells. The semiconductor test circuit is provided with a write data generating circuit for generating a plurality of internal write data signals to be written into the plurality of memory cells of one unit of write mask according to an external write data signal, an internal expected value generating circuit for generating a plurality of internal expected value signals based on a read data signal from a predetermined memory cell among the plurality of memory cells, and a determination circuit for determining whether the logic levels of a plurality of read data signals from the plurality of memory cells and the logic levels of the plurality of internal expected value signals generated in the internal expected value generating circuit respectively match or not, and outputting a signal of a first level when the logic levels match in all respective pairs, and outputting a signal of a second level when the logic levels do not match at least in one pair. Thus, the plurality of internal expected values are generated based on a read data signal from a predetermined memory cell among the plurality of memory cells, and match/mismatch of the read data signals and the internal expected values is determined per unit of write mask so that the multi-bit test can be performed even when the test pattern is written using the write mask function.
Preferably, the write data generating circuit includes a plurality of registers each of which holds and outputs a data signal supplied in advance, and a plurality of first logical circuits which are respectively provided corresponding to the plurality of registers and each of which generates an exclusive-OR signal of the external write data signal and an output signal of a corresponding register and outputs the generated exclusive-OR signal as the internal write data signal. In this case, a desired test pattern can be written into the plurality of memory cells by storing a plurality of data signals in the plurality of registers in a desired pattern.
More preferably, the internal expected value generating circuit includes a second logical circuit for generating an exclusive-OR signal of a read data signal from the predetermined memory cell and an output data signal from a register corresponding to the predetermined memory cell, and a plurality of third logical circuits which are respectively provided corresponding to the plurality of registers and each of which generates an exclusive-OR signal of the exclusive-OR signal generated in the second logical circuit and an output data signal of a corresponding register and outputs the generated exclusive-OR signal as the internal expected value signal. In this case, when the memory cell is normal, the logic level of the internal expected value signal would be the same as the logic level of the internal write data signal.
More preferably, the internal expected value generating circuit further includes a switching circuit for selecting one of the external expected value signal and the exclusive-OR signal generated in the second logical circuit according to a switching signal, and each of the plurality of third logical circuits generates an exclusive-OR signal of a signal selected by the switching circuit and an output data signal from a corresponding register and outputs the generated exclusive-OR signal as the internal expected value signal. In this case, when the test pattern is written without using the write mask function, a more accurate multi-bit test result can be obtained by selecting the external expected value signal.
More preferably, the determination circuit includes a plurality of sub-determination circuits which are respectively provided corresponding to the plurality of third logical circuits and each of which determines whether the logic level of a read data signal from a corresponding memory cell matches the logic level of an internal expected value signal output from a corresponding third logical circuit, and outputs a first signal when the logic levels match, and outputs a second signal when the logic levels do not match; and a determination result compressing circuit for outputting a signal of the first level when the first signal is output from all of the plurality of sub-determination circuits and for outputting a signal of the second level when the second signal is output from at least one of the plurality of sub-determination circuits. In this case, the determination circuit can be configured with ease.
More preferably, the semiconductor memory device has a function simultaneously to perform writing/reading of data signals of Mxc3x97N (here, each of M and N is an integer greater than or equal to 2) memory cells designated by an address signal as well as a write mask function to inhibit rewriting of the data signals of the Mxc3x97N memory cells per unit of write mask including N memory cells. The write data generating circuit generates Mxc3x97N internal write data signals to be written into the Mxc3x97N memory cells according to the external write data signal. The internal expected value generating circuit is provided corresponding to each unit of write mask for generating N internal expected value signals based on a read data signal from a predetermined memory cell among the corresponding N memory cells. The determination circuit is provided corresponding to each unit of write mask for determining whether logic levels of N read data signals from the corresponding N memory cells and logic levels of N internal expected value signals generated in the corresponding internal expected value generating circuit respectively match or not. In this case, a multi-bit test can be performed even when a test pattern is written using a write mask function for one unit of write mask of M units of write mask.
In addition, another semiconductor test circuit according to the present invention is a circuit for testing a semiconductor memory device having a function simultaneously to perform writing/reading of data signals of a plurality of memory cells designated by an address signal and having a write mask function to inhibit rewriting of data signals of the plurality of memory cells. The semiconductor test circuit is provided with a write data generating circuit for generating a plurality of internal write data signals to be written into the plurality of memory cells of one unit of write mask according to an external write data signal, a plurality of signal regeneration circuits which respectively receive a plurality of read data signals from the plurality of memory cells and each of which regenerates the external write data signal based on the received read data signal, and a determination circuit for determining whether the logic levels of a plurality of external write data signals regenerated by the plurality of signal regeneration circuits all match or not, and outputting a signal of a level according to a determination result. Thus, the plurality of external write data signals are regenerated based on the plurality of read data signals from the plurality of memory cells of one unit of write mask, and match/mismatch of the regenerated plurality of external write data signals is determined, so that the multi-bit test can be performed even when the test pattern is written using the write mask function.
Preferably, the write data generating circuit includes a plurality of registers each of which holds and outputs a data signal supplied in advance, and a plurality of first logical circuits which are respectively provided corresponding to the plurality of registers and each of which generates an exclusive-OR signal of the external write data signal and an output signal of a corresponding register and outputs the generated exclusive-OR signal as the internal write data signal. In this case, a desired test pattern can be written into the plurality of memory cells by storing a plurality of data signals in the plurality of registers in a desired pattern.
More preferably, the signal regeneration circuit includes a second logical circuit for generating an exclusive-OR signal of a read data signal from a corresponding memory cell and an output signal from a corresponding register and supplying the generated exclusive-OR signal as the external write data signal to the determination circuit. In this case, the external write data signal can be regenerated with ease.
More preferably, the semiconductor memory device has a function simultaneously to perform writing/reading of data signals of Mxc3x97N (here, each of M and N is an integer greater than or equal to 2) memory cells designated by an address signal as well as a write mask function to inhibit rewriting of the data signals of the Mxc3x97N memory cells per unit of write mask including N memory cells. The write data generating circuit generates Mxc3x97N internal write data signals to be written into the Mxc3x97N memory cells according to the external write data signal. The semiconductor test circuit includes Mxc3x97N signal regeneration circuits corresponding to the Mxc3x97N memory cells, respectively. Each of the signal regeneration circuits regenerates the external write data signal based on a read data signal from a corresponding memory cell. The determination circuit is provided corresponding to each unit of write mask for determining whether logic levels of N external write data signals regenerated by the corresponding N signal regeneration circuits all match or not. In this case, a multi-bit test can be performed even when a test pattern is written using a write mask function for one unit of write mask of M units of write mask.
The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.